MC9S08DZ96F2CLL datasheet(77/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

Table 4-13. FCDIV Register Field Descriptions

Field

Description

DIVLD

Divisor Loaded Status Flag — When set, this read-only status ﬂag indicates that the FCDIV register has been

written since reset. Reset clears this bit and the ﬁrst write to this register causes this bit to become set regardless

of the data written.

0 FCDIV has not been written since reset; erase and program operations disabled for FLASH and EEPROM.

1 FCDIV has been written since reset; erase and program operations enabled for FLASH and EEPROM.

PRDIV8

Prescale (Divide) FLASH and EEPROM Clock by 8 (This bit is write once.)

0 Clock input to the FLASH and EEPROM clock divider is the bus rate clock.

1 Clock input to the FLASH and EEPROM clock divider is the bus rate clock divided by 8.

5:0

DIV

Divisor for FLASH and EEPROM Clock Divider — The FLASH and EEPROM clock divider divides the bus rate

clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV ﬁeld plus one. The resulting

frequency of the internal FLASH and EEPROM clock must fall within the range of 200 kHz to 150 kHz for proper

FLASH and EEPROM operations. Program/Erase timing pulses are one cycle of this internal FLASH and

EEPROM clock which corresponds to a range of 5

μs to 6.7 μs. The automated programming logic uses an

integer number of these pulses to complete an erase or program operation. See Equation 4-1 and Equation 4-2.

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