MC9S08DZ96F2CLL datasheet(87/458 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either

background debug mode or stop mode and begins from zero upon exit from background debug mode or

stop mode.

5.5

Interrupts

Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine

(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other

than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events

such as an edge on the IRQ pin or a timer-overﬂow event. The debug module can also generate an SWI

under certain circumstances.

If an event occurs in an enabled interrupt source, an associated read-only status ﬂag will become set. The

CPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCR

is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which

prevents all maskable interrupt sources. The user program initializes the stack pointer and performs other

system setup before clearing the I bit to allow the CPU to respond to interrupts.

When the CPU receives a qualiﬁed interrupt request, it completes the current instruction before responding

to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and

consists of:

•

Saving the CPU registers on the stack

•

Setting the I bit in the CCR to mask further interrupts

•

Fetching the interrupt vector for the highest-priority interrupt that is currently pending

•

Filling the instruction queue with the ﬁrst three bytes of program information starting from the

address fetched from the interrupt vector locations

While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another

interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0

when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be cleared

inside an ISR (after clearing the status ﬂag that generated the interrupt) so that other interrupts can be

serviced without waiting for the ﬁrst service routine to ﬁnish. This practice is not recommended for anyone

other than the most experienced programmers because it can lead to subtle program errors that are difﬁcult

to debug.

The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,

A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the

stack.

NOTE

For compatibility with M68HC08 devices, the H register is not

automatically saved and restored. It is good programming practice to push

H onto the stack at the start of the interrupt service routine (ISR) and restore

it immediately before the RTI that is used to return from the ISR.

If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced ﬁrst

(see Table 5-1).

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