MC9S08DZ96F2CLL datasheet(96/458 Pages) FREESCALE

96 / 458 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.8.4

System Options Register 1 (SOPT1)

This high page register is a write-once register so only the ﬁrst write after reset is honored. It can be read

at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to

avoid accidental changes to these sensitive settings. This register should be written during the user’s reset

initialization program to set the desired controls even if the desired settings are the same as the reset

settings.

76543210

COPT

STOPE

SCI2PS

IIC1PS

000

Reset:

11000000

= Unimplemented or Reserved

Figure 5-5. System Options Register 1 (SOPT1)

Table 5-5. SOPT1 Register Field Descriptions

Field

Description

7:6

COPT[1:0]

COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with

COPCLKS in SOPT2 deﬁnes the COP timeout period. See Table 5-6.

STOPE

Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user

program attempts to execute a STOP instruction, an illegal opcode reset is forced.

0 Stop mode disabled.

1 Stop mode enabled.

SCI2PS

SCI2 Pin Select— This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module.

0 TxD2 on PTF0, RxD2 on PTF1.

1 TxD2 on PTE6, RxD2 on PTE7.

IIC1PS

IIC1 Pin Select— This write-once bit selects the location of the SCL1 and SDA1 pins of the IIC1 module.

0 SCL1 on PTF2, SDA1 on PTF3.

1 SCL1 on PTE4, SDA1 on PTE5.

Table 5-6. COP Conﬁguration Options

Control Bits

Clock Source

COP Window1 Opens

(COPW = 1)

1 Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column

displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode

(COPW = 1).

COP Overﬂow Count

COPCLKS

COPT[1:0]

N/A

0:0

N/A

COP is disabled

0:1

1 kHz

N/A

25 cycles (32 ms2)

2 Values shown in milliseconds based on t

LPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing,” for the

tolerance of this value.

1:0

1 kHz

N/A

28 cycles (256 ms1)

1:1

1 kHz

N/A

210 cycles (1.024 s1)

0:1

Bus

6144 cycles

213 cycles

1:0

Bus

49,152 cycles

216 cycles

1:1

Bus

196,608 cycles

218 cycles

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