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MC9S08DZ96F2CLL bảng dữ liệu(PDF) 67 Page - Freescale Semiconductor, Inc

tên linh kiện MC9S08DZ96F2CLL
Giải thích chi tiết về linh kiện  Microcontrollers
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MC9S08DZ96F2CLL bảng dữ liệu(HTML) 67 Page - Freescale Semiconductor, Inc

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Chapter 4 Memory
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
67
4.6
FLASH and EEPROM
MC9S08DZ128 Series devices include FLASH and EEPROM memory intended primarily for program
and data storage. In-circuit programming allows the operating program and data to be loaded into FLASH
and EEPROM, respectively, after final assembly of the application product. It is possible to program the
arrays through the single-wire background debug interface. Because no special voltages are needed for
erase and programming operations, in-application programming is also possible through other
software-controlled communication paths. For a more detailed discussion of in-circuit and in-application
programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor
document order number HCS08RMv1.
4.6.1
Features
Features of the FLASH and EEPROM memory include:
•
Up to 128K of FLASH and up to 2K of EEPROM (see Table 1-1 for exact array sizes)
•
FLASH sector size: 512 bytes
•
EEPROM sector size: selectable 4-byte or 8-byte sector mapping operation
•
Single power supply program and erase
•
Command interface for fast program and erase operation
•
Up to 100,000 program/erase cycles at typical voltage and temperature
•
Flexible block protection
•
Security feature for FLASH, EEPROM, and RAM
•
Burst programming capability
•
Sector erase abort
4.6.2
Program and Erase Times
Before any program or erase command can be accepted, the FLASH and EEPROM clock divider register
(FCDIV) must be written to set the internal clock for the FLASH and EEPROM module to a frequency
(fFCLK) between 150 kHz and 200 kHz (see Section 4.6.11.1, “FLASH and EEPROM Clock Divider
Register (FCDIV)”). This register can be written only once, so normally this write is performed during
reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register.
One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase
pulses. An integer number of these timing pulses is used by the command processor to complete a program
or erase command.
NOTE
When changing from a low power mode (Stop2 mode or bus frequency less
than 150kHz) into an operating condition that allows program or erase, it is
necessary to wait at least 10
μs before starting a program or erase command.



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