MC9S08DZ96F2CLL datasheet(41/458 Pages) FREESCALE

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Chapter 3 Modes of Operation

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

3.6

Stop Modes

One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1

leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV2),” for

more information.

Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various

conditions. The selected mode is entered following the execution of a STOP instruction.

3.6.1

Stop3 Mode

Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The

states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.

Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt

pins are IRQ, PIA0–PIA7, PIB0–PIB7, PID0–PID7, and PIJ0–PIJ7. Exit from stop3 can also be done by

the low voltage detection (LVD) reset, the low voltage warning (LVW) interrupt, the ADC conversion

complete interrupt, the analog comparator interrupt, the real-time clock (RTC) interrupt, the MSCAN

wake-up interrupt, or the SCI receiver interrupt.

If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after

fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate

interrupt vector.

3.6.1.1

LVD Enabled in Stop3 Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below

the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time

the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.

For the ADC to operate or for the ACMP to be used when comparing with an internal voltage, the LVD

must be left enabled when entering stop3.

Table 3-1. Stop Mode Selection

STOPE

ENBDM 1

1 ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see the Development Support chapter.

LVDE

LVDSE

PPDC

Stop Mode

Stop modes disabled; illegal opcode reset if STOP instruction executed

Stop3 with BDM enabled 2

2 When in Stop3 mode with BDM enabled, The S

IDD will be near RIDD levels because internal clocks are enabled.

Both bits must be 1

3 If LVD = 1 in stop, the MCU enters stop3, regardless of the conﬁguration of PPDC.

Stop3 with voltage regulator active

Either bit a 0

Stop3

Either bit a 0

Stop2

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