MC9S08DZ96F2CLL datasheet(60/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

Nonvolatile FLASH registers, shown in Table 4-5, are located in the FLASH memory. These registers

include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory

resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the

FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page

registers to control security and block protection options.

The factory MCG trim value is stored in a nonvolatile location and will be loaded into the MCGTRM and

MCGSC registers after any reset if not in a BDM mode. If in a BDM mode, a default value of 0x80 is

loaded. The internal reference trim values stored in Flash (0xFFAE, 0xFFAF), TRIM and FTRIM, can be

programmed by third party programmers and must be copied into the corresponding MCG registers by

user code to override the factory trim.

Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily

disengage memory security. This key mechanism can be accessed only through user code running in secure

memory. (A security key cannot be entered directly through background debug commands.) This security

key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the

only way to disengage security is by mass erasing the FLASH if needed (normally through the background

0x18B3

CANTIDR3

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR4

0x18B4 –

0x18BB

CANTDSR0 –

CANTDSR7

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0x18BC

CANTDLR

—

DLC3

DLC2

DLC1

DLC0

0x18BD

CANTTBPR

PRIO7

PRIO6

PRIO5

PRIO4

PRIO3

PRIO2

PRIO1

PRIO0

0x18BE

CANTTSRH

TSR15

TSR14

TSR13

TSR12

TSR11

TSR10

TSR9

TSR8

0x18BF

CANTTSRL

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

1 SRR and IDE are both 1s.

2 The position of RTR differs between extended and standard identiﬁer mapping.

3 SRR and IDE are both 1s.

4 The position of RTR differs between extended and standard identiﬁer mapping.

Table 4-5. Nonvolatile Register Summary

Address

Bit 7

654321

Bit 0

0xFFAE

Reserved for

storage of FTRIM

FTRIM

0xFFAF

Reserved for

storage of

MCGTRM

TRIM

0xFFB0–

0xFFB7

NVBACKKEY

8-Byte Comparison Key

0xFFB8–

0xFFBC

Reserved

—

0xFFBD

NVPROT

EPS

FPS

FPOP

0xFFBE

Reserved

—

0xFFBF

NVOPT

KEYEN

FNORED

EPGMOD

SEC

Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts — Extended Mapping Shown

(Sheet 2 of 2)

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