MC9S08DZ96F2CLL datasheet(65/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

address of the FLASH memory location to be addressed. When accessing data using LBP, the contents of

LAP2:LAP0 will increment after the read or write is complete.

Accessing LBP does the same thing as accessing LWP. The MMU register ordering of LWP followed by

LBP, allow the user to access data by words using the LDHX or STHX instructions with the address of the

LWP register.

4.4.3.5

Linear Byte Register (LB)

This register is one of three data registers that the user can use to access any FLASH memory location in

the extended address map. When LB is accessed the contents of LAP2:LAP0 make up the extended

address of the FLASH memory location to be addressed.

4.4.3.6

Linear Address Pointer Add Byte Register (LAPAB)

The user can increase or decrease the contents of LAP2:LAP0 by writing a 2s complement value to

LAPAB. The value written will be added to the current contents of LAP2:LAP0.

76543210

Reset:

Figure 4-8. Linear Byte Post Increment Register (LBP)

Table 4-9. Linear Byte Post Increment Register Field Descriptions

Field

Description

7:0

D7:D0

Reads of this register will ﬁrst return the data value pointed to by the linear address pointer, LAP2:LAP0 and then

will increment LAP2:LAP0. Writes to this register will ﬁrst write the data value to the memory location speciﬁed

by the linear address pointer and then will increment LAP2:LAP0. Writes to this register are most commonly used

when writing to the FLASH block(s) during programming.

76543210

Reset:

Figure 4-9. Linear Byte Register (LB)

Table 4-10. Linear Data Register Field Descriptions

Field

Description

7:0

D7:D0

Reads of this register returns the data value pointed to by the linear address pointer, LAP2:LAP0. Writes to this

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