MC9S08DZ96F2CLL datasheet(182/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

182

Freescale Semiconductor

•

BDM mode is not active

In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock.

The external reference clock which is enabled can be an external crystal/resonator or it can be another

external clock source.

The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available

for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed

external modes as determined by the state of the PLLS bit.

In this mode, the DRST bit reads 0 regardless of whether the DRS bit is set to 1 or 0.

8.4.1.9

Stop

Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled

and all MCG clock signals are static except in the following cases:

MCGIRCLK will be active in stop mode when all the following conditions occur:

•

IRCLKEN = 1

•

IREFSTEN = 1

MCGERCLK will be active in stop mode when all the following conditions occur:

•

ERCLKEN = 1

•

EREFSTEN = 1

8.4.2

Mode Switching

The IREFS bit can be changed at anytime, but the actual switch to the newly selected clock is shown by

the IREFST bit. When switching between engaged internal and engaged external modes, the FLL or PLL

will begin locking again after the switch is completed.

For the special case of entering stop mode immediately after switching to FBE mode, if the external clock

and the internal clock are disabled in stop mode, (EREFSTEN = 0 and IREFSTEN = 0), it is necessary to

allow 100us after the IREFST bit is cleared to allow the internal reference to shutdown. For most cases the

delay due to instruction execution times will be sufﬁcient.

The CLKS bits can also be changed at anytime, but the actual switch to the newly selected clock is shown

by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected.

The DRS bits can be changed at anytime except when LP bit is 1. If the DRS bits are changed while in

FLL engaged internal (FEI) or FLL engaged external (FEE), the bus clock remains at the previous DCO

range until the new DCO starts. When the new DCO starts the bus clock switches to it. After switching to

the new DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time

is over, the FLL is locked. The completion of the switch is shown by the DRST bits.

For details see Figure 8-9.

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