MC9S08DZ96F2CLL datasheet(183/458 Pages) FREESCALE

183 / 458 page

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

183

8.4.3

Bus Frequency Divider

The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur

immediately.

8.4.4

Low Power Bit Usage

The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when

these systems are not being used. The DRS bit can not be written while LP bit is 1.However, in some

applications it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy

before switching to an engaged mode. Do this by writing the LP bit to 0.

8.4.5

Internal Reference Clock

When IRCLKEN is set the internal reference clock signal will be presented as MCGIRCLK, which can be

used as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period

of the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM

the MCGTRM register will increase the MCGIRCLK frequency. The TRIM bits will effect the MCGOUT

frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low

power internal (BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by other

resets.

Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in

MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock

timing speciﬁcations (see the Device Overview chapter).

If IREFSTEN and IRCLKEN bits are both set, the internal reference clock will keep running during stop

mode in order to provide a fast recovery upon exiting stop.

8.4.6

External Reference Clock

The MCG module can support an external reference clock with frequencies between 31.25 kHz to 40 MHz

in all modes. When ERCLKEN is set, the external reference clock signal will be presented as

MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference

clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the

frequency can be equal to the maximum frequency the chip-level timing speciﬁcations will support (see

the Device Overview chapter).

If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode,

the external reference clock will keep running during stop mode in order to provide a fast recovery upon

exiting stop.

If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain

frequency (floc_high or floc_low depending on the RANGE bit in the MCGC2), the MCU will reset. The LOC

bit in the System Reset Status (SRS) register will be set to indicate the error.

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