MC9S08DZ96F2CLL datasheet(187/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

187

reference can achieve a high-range maximum DCO output of 39.85 MHz with a multiplier of 1216. When

the DRS bit is clear, the 32.768 kHz reference can achieve a mid-range maximum DCO output of 19.92

MHz with a multiplier of 608.

In FBI and FEI modes, setting the DMX32 bit is not recommended. If the internal reference is trimmed to

a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the

microcontroller system clock out of speciﬁcation and damage the part.

8.5.3

MCG Mode Switching

When switching between operational modes of the MCG, certain conﬁguration bits must be changed in

order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,

CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or

OSCINIT) must be checked before moving on in the application software.

Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the

mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001

(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required

frequency between 1 and 2 MHz.

If switching to FBE or FEE mode, ﬁrst setting the DIV32 bit will ensure a proper reference frequency is

sent to the FLL clock at all times.

In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor

between 1024 and 512 with the DRS bit in MCGT. Writes to DRS will be ignored if LP=1 or PLLS=1.

The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or

PLL clock has an appropriate reference clock frequency to switch to. The table below shows MCGOUT

frequency calculations using RDIV, BDIV, and VDIV settings for each clock mode. The bus frequency is

equal to MCGOUT divided by 2.

Table 8-10. MCGOUT Frequency Calculation Options

Clock Mode

fMCGOUT

Note

FEI (FLL engaged internal)

(fint * F ) / B

Typical fMCGOUT = 16 MHz

immediately after reset.

FEE (FLL engaged external)

(fext / R *F) / B

fext / R must be in the range of

31.25 kHz to 39.0625 kHz

FBE (FLL bypassed external)

fext / B

fext / R must be in the range of

31.25 kHz to 39.0625 kHz

FBI (FLL bypassed internal)

fint / B

Typical fint = 32 kHz

PEE (PLL engaged external)

[(fext / R) * M] / B

fext / R must be in the range of 1

MHz to 2 MHz

PBE (PLL bypassed external)

fext / B

fext / R must be in the range of 1

MHz to 2 MHz

BLPI (Bypassed low power internal)

fint / B

BLPE (Bypassed low power external)

fext / B

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