MC9S08DZ96F2CLL datasheet(191/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

191

8.5.3.2

Example # 2: Moving from PEE to BLPI Mode: Bus Frequency =16 kHz

In this example, the MCG will move through the proper operational modes from PEE mode with an 8MHz

crystal conﬁgured for an 16 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus

frequency.First, the code sequence will be described. Then a ﬂowchart will be included which illustrates

the sequence.

1. First, PEE must transition to PBE mode:

a) MCGC1 = 0x98 (%10011000)

– CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external

reference clock

b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference

clock is selected to feed MCGOUT

2. Then, PBE must transition either directly to FBE mode or ﬁrst through BLPE mode and then to

FBE mode:

a) BLPE: If a transition through BLPE mode is desired, ﬁrst set LP (bit 3) in MCGC2 to 1

b) BLPE/FBE: MCGC3 = 0x18(%00011000)

– PLLS (bit 6) clear to 0 to select the FLL. At this time, with an RDIV value of %011, the PLL

reference divider of 8 is switched to an FLL divider of 256 (see Table 8-2), resulting in a

reference frequency of 8 MHz / 256 = 31.25 kHz. If RDIV was not previously set to %011

(necessary to achieve required 31.25-39.06 kHz FLL reference frequency with an 8 MHz

external source frequency), it must be changed prior to clearing the PLLS bit. In BLPE

mode,changing this bit only prepares the MCG for FLL usage in FBE mode. With PLLS =

0, the VDIV value does not matter.

– DIV32 (bit 4) set to 1 (if previously cleared), automatically switches RDIV bits to the proper

reference divider for the FLL clock (divide-by-256)

c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to

FBE mode

d) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the

PLLS clock is the FLL

e) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has

acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running.

3. Next, FBE mode transitions into FBI mode:

a) MCGC1 = 0x5C (%01011100)

– CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the

internal reference clock

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