MC9S08DZ96F2CLL datasheet(194/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

194

Freescale Semiconductor

8.5.3.3

Example #3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz,

Bus Frequency = 16 MHz

In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz

bus frequency running off of the internal reference clock (see previous example) to FEE mode using an

8MHz crystal conﬁgured for a 16 MHz bus frequency. First, the code sequence will be described. Then a

ﬂowchart will be included which illustrates the sequence.

1. First, BLPI must transition to FBI mode.

a) MCGC2 = 0x00 (%00000000)

– LP (bit 3) in MCGSC is 0

b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired

lock. Although the FLL is bypassed in FBI mode, it is still enabled and running.

2. Next, FBI will transition to FEE mode.

a) MCGC2 = 0x36 (%00110110)

– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range

– HGO (bit 4) set to 1 to conﬁgure external oscillator for high gain operation

– EREFS (bit 2) set to 1, because a crystal is being used

– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active

b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit

has been initialized.

c) MCGC1 = 0x18 (%00011000)

– CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock

source

– RDIV (bits 5-3) remain at %011, or divide-by-256 for a reference of 8 MHz / 256 = 31.25

kHz.

– IREFS (bit 1) cleared to 0, selecting the external reference clock

d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current

source for the reference clock

e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has

reacquired lock.

f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is

selected to feed MCGOUT

g) Now, with a 31.25 kHz reference frequency, a ﬁxed DCO multiplier of 1024, and a bus divider

of 1, MCGOUT = 31.25 kHz * 1024 / 1 = 32 MHz. Therefore, the bus frequency is 16 MHz.

h) At this point, by default, DRS (bit 0) in MCGT is set to 1 and DMX32 (bit 5) in MCGT is

cleared to 0. If a bus frequency of 8 MHz is desired instead, clear DRS to 0 to switch the FLL

multiplication factor from 1024 to 512 and loop until LOCK (bit 6) in MCGSC is set, indicating

that the FLL has reacquired LOCK. To return the bus frequency to 16 MHz, set DRS to 1 again,

and the FLL multiplication factor will switch back to 1024. Then loop again until the LOCK

bit is set.

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