MC9S08DZ96F2CLL datasheet(195/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

195

Figure 8-12. Flowchart of BLPI to FEE Mode Transition using an 8 MHz crystal

8.5.4

Calibrating the Internal Reference Clock (IRC)

The IRC is calibrated by writing to the MCGTRM register ﬁrst, then using the FTRIM bit to “ﬁne tune”

the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where

the FTRIM bit is the LSB.

The trim value after reset is the factory trim value unless the device resets into any BDM mode in which

case it is 0x800. Writing a larger value will decrease the frequency and smaller values will increase the

frequency. The trim value is linear with the period, except that slight variations in wafer fab processing

produce slight non-linearities between trim value and period. These non-linearities are why an iterative

MCGC2 = $36

CHECK

OSCINIT = 1 ?

MCGC1 = $18

CHECK

IREFST = 0?

CHECK

CLKST = %00?

CONTINUE

IN FEE MODE

START

IN BLPI MODE

YES

MCGC2 = $00

OPTIONAL:

CHECK LOCK

= 1?

YES

OPTIONAL:

CHECK LOCK

= 1?

YES

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