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MC9S08DZ96F2CLL bảng dữ liệu(PDF) 213 Page - Freescale Semiconductor, Inc

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MC9S08DZ96F2CLL bảng dữ liệu(HTML) 213 Page - Freescale Semiconductor, Inc

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
213
10.2.1
Analog Power (VDDAD)
The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected
internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD.
External filtering may be necessary to ensure clean VDDAD for good results.
10.2.2
Analog Ground (VSSAD)
The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected
internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.
10.2.3
Voltage Reference High (VREFH)
VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to
VDDAD. If externally available, VREFH may be connected to the same potential as VDDAD or may be driven
by an external source between the minimum VDDAD spec and the VDDAD potential (VREFH must never
exceed VDDAD).
10.2.4
Voltage Reference Low (VREFL)
VREFL is the low-reference voltage for the converter. In some packages, VREFL is connected internally to
VSSAD. If externally available, connect the VREFL pin to the same voltage potential as VSSAD.
10.2.5
Analog Channel Inputs (ADx)
The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through the
ADCH channel select bits.
10.3
Register Definition
These memory-mapped registers control and monitor operation of the ADC:
•
Status and control register, ADCSC1
•
Status and control register, ADCSC2
•
Data result registers, ADCRH and ADCRL
•
Compare value registers, ADCCVH and ADCCVL
•
Configuration register, ADCCFG
•
Pin control registers, APCTL1, APCTL2, APCTL3
10.3.1
Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).



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