ADC32RF83 datasheet(122/138 Pages) TI

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NSD

CLK

ADC

dBc / Hz

log

ADC Noise Floor

Inband Blocker

Clock Phase Noise

Modulated Onto the Blocker

Wanted Signal

2 u fS

fmin

Integration Bandwidth

Frequency Offset

Clock Phase Noise

122

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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9.1.3.1 External Clock Phase Noise Consideration

External clock jitter can be calculated by integrating the phase noise of the clock source out to approximately two

times of the ADC sampling rate (2 × fS), as shown in Figure 255. In order to maximize the ADC SNR, an external

band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the

broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the

band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a

certain input frequency.

Figure 255. Integration Bandwidth for Extracting Jitter from Clock Phase Noise

However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity,

the phase noise information can be used directly to estimate the noise budget contribution at a certain offset

frequency, as shown in Figure 256.

Figure 256. Small Wanted Signal in Presence of Interferer

At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example,

the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the

signal band of interest is too large, the wanted signal cannot not be recovered.

The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and

frequency of the input signal. The ADC sampling rate scales the clock phase noise, as shown in Equation 8.

(8)

Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock

can be calculated.

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