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PCI9060ES bảng dữ liệu(PDF) 108 Page - List of Unclassifed Manufacturers

tên linh kiện PCI9060ES
Giải thích chi tiết về linh kiện  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
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PCI9060ES bảng dữ liệu(HTML) 108 Page - List of Unclassifed Manufacturers

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SECTION 5
PCI 9080
PIN DESCRIPTION
©PLX Technology, Inc., 1997
Page 99
Version 1.02
Table 5-8. S Bus Mode Interface Pin Description (continued)
S Bus Mode
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
LLOCK#
Bus Lock
1
I
153
Indicates an atomic operation that may require multiple transactions
to complete. Used by the PCI 9080 for direct local access to the PCI
bus.
LRESETo#
Local Bus Reset Out
1
O
TP
8 mA
11
Asserted when the PCI 9080 chip is reset.
Note:
For i960®S processors, this output must be used to drive
the Reset Input of the i960®S processor. This enables PCI 9080 to
determine the phase of the 2x clock processor.
LW/R#
Write/Read
1
I/O
TS
12 mA
137
Asserted low for reads and high for writes.
READYi#
Ready In
1
I
147
When the PCI 9080 is a bus master, READYi# is used to indicate
read data on the bus is valid or a write data transfer is complete.
READYi# is used in conjunction with the PCI 9080 programmable wait
state generator.
READYo#
Ready Out
1
O
DTS
8 mA
148
When a local bus access is made to the PCI 9080, indicates that read
data on the bus is valid or that a write data transfer is complete.
READYo# can be connected to READYi#.
EOT0#
End of Transfer for
DMA Ch 0
1
I
4
Terminates the current DMA Ch 0 transfer.
EOT1#
End of Transfer for
DMA Ch 1
1
I
5
Terminates the current DMA Ch 1 transfer.



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