SPC574K72E5 datasheet(110/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

—

Bus free time between Start and Stop condition

4.7

—

µs

—

Data hold time

0.0

—

Clock high time

—

PER_CLK Cycle

—

Data setup time

0.0

—

Start condition setup time (for repeated start condition only)

—

PER_CLK Cycle

—

Stop condition setup time

—

PER_CLK Cycle

I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than

1 ns (10%

– 90%).

PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the

device reference manual for more detail.

Table 62. I2C input timing specifications — SCL and SDA(1)(Continued)

No.

Symbol

Parameter

Value

Unit

Min

Max

Table 63. I2C output timing specifications — SCL and SDA(1)(2)(3)(4)

No.

Symbol

Parameter

Value

Unit

Min

Max

—

Start condition hold time

—

PER_CLK

Cycle(5)

—

Clock low time

—

PER_CLK Cycle

—

Bus free time between Start and Stop condition

4.7

—

µs

—

Data hold time

—

PER_CLK Cycle

—

Clock high time

—

PER_CLK Cycle

—

Data setup time

—

PER_CLK Cycle

—

Start condition setup time (for repeated start condition

only)

—

PER_CLK Cycle

—

Stop condition setup time

—

PER_CLK Cycle

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speedsand may

cause incorrect operation.

Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output

timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.

The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.

PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the

device reference manual for more detail.

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