SPC574K72E5 datasheet(47/127 Pages) STMICROELECTRONICS

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DocID023601 Rev 5

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SPC574Kxx

Electrical characteristics

126



PLL0LTJIT

PLL0 long-term jitter(3)

fPLL0IN = 20 MHz

(resonator), VCO

frequency = 800 MHz

10 periods accumulated

jitter (80 MHz equivalent

frequency), 6-sigma pk-pk

—

± 250

16 periods accumulated

jitter (50 MHz equivalent

frequency), 6-sigma pk-pk

—

± 300

long term jitter (< 1 MHz

equivalent frequency), 6-

sigma pk-pk

—

± 500

IPLL0

PLL0 consumption

FINE LOCK state

—

fPLL0FREE

VCO free running

frequency

—

400

MHz

PLL0IN clock retrieved directly from either internal RC oscillator (IRCOSC) or external oscillator (XOSC) clock. Input

characteristics are granted when using XOSC.

fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range

8 MHz-20 MHz.

VDD_LV noise due to application in the range VDD_LV = 1.25 V ± 5%, with frequency below PLL bandwidth (40 KHz) is

filtered.

Table 22. PLL0 electrical characteristics(Continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

Table 23. PLL1 electrical characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

fPLL1IN

SR — PLL1 input clock(1)

—38

—

MHz



PLL1IN

SR — PLL1 input clock duty cycle(1)

—35

—

fPLL1VCO CC P PLL1 VCO frequency

—

600

—

1250

MHz

fPLL1PHI CC D PLL1 output clock frequency on PHI

—

4.762

—

160

MHz

tPLL1LOCK CC P PLL1 lock time

—

100

µs

fPLL1MOD CC T PLL1 modulation frequency

—

250

KHz



PLL1MOD CC T PLL1 modulation depth (when enabled) Center spread

0.25

—

Down spread

0.5

—

IPLL1

CC T PLL1 consumption

FINE LOCK state

—

fPLL1FREE CC D VCO free running frequency

—

400

MHz

PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when

using internal PLL0 or XOSC is used in functional mode.

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