| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
SPC574K72E5 bảng dữ liệu(PDF) 76 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC574K72E5 bảng dữ liệu(HTML) 76 Page - STMicroelectronics |
|
76 / 127 page ![]() Electrical characteristics SPC574Kxx 76/127 DocID023601 Rev 5 During power-up, all functional terminals are maintained in a known state as described in the following table. 3.16 Flash memory electrical characteristics Table 40 shows the estimated Program/Erase characteristics. 3. ADC performance is not guaranteed when ALTREFn, and VDD_HV_ADR supplies are above VDD_HV_IO/VDD_HV_ADV. Table 39. Functional terminals state during power-up and reset TERMINAL type(1) POWER-UP(2) pad state RESET pad state DEFAULT pad state (3) Comments PORST Strong pull- down(4) Weak pull-down Weak pull-down Power-on reset pad ESR0(5) Strong pull-down Strong pull-down Weak pull-up Functional reset pad ESR1 Weak pull-up Weak pull-up Weak pull-up — TEST_MODE Weak pull-down Weak pull-down(6) Weak pull-down(6) — GPIO Weak pull-up(4) Weak pull-up Weak pull-up — ANALOG High impedance High impedance High impedance — ERROR[0] High impedance High impedance High impedance During functional reset, pad state can be overridden by FCCU TRST High impedance Weak pull-down Weak pull-down — TCK High impedance Weak pull-down Weak pull-down — TMS Weak pull-up Weak pull-up Weak pull-up — TDI Weak pull-up Weak pull-up Weak pull-up — TDO High impedance High impedance High impedance — 1. Refer to pinout information for terminal type. 2. POWER-UP state is guaranteed from VDD_HV_IO > VDD_POR and maintained until supply crosses the power-on reset thresholds VPORUP_LV for LV supply and VPORUP_HV for high voltage supply. 3. Before software configuration. 4. Pull-down and pull-up strengths are provided in Table 15 (I/O pull-up/pull-down DC electrical characteristics) 5. Unlike ESR0, ESR1 is provided as a normal GPIO and implements weak pull-up during power-up. 6. An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the package TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to VSS_HV_IO on the board for maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and has no affect afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up. The TESTMODE pin can be connected externally directly to ground without any other components. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |