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1 / 127 page  This is information on a product in full production. July 2015 DocID023601 Rev 5 1/127 SPC574K70E5, SPC574K72E5 32-bit Power Architecture® based MCU for automotive applications Datasheet - production data Features Two main 32-bit Power Architecture® VLE compliant CPU core (e200z4), dual issue, running in lockstep – Single-precision floating point operations – 16 KB local instruction SRAM and 64 KB local data SRAM – 4 KB I-Cache and 2 KB D-Cache One 32-bit Power Architecture® VLE compliant I/O processor core (e200z2) – Single-precision floating point operations – Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction support for digital signal processing (DSP) – 16 KB local instruction SRAM and 48 KB local data SRAM 2624 KB on-chip flash memory – Supporting EEPROM emulation (64 KB) 64 KB on-chip general-purpose SRAM (+112 KB data RAM included in the CPUs) Multi-channel direct memory access controller (eDMA) with 32 channels Dual interrupt controller (INTC) Dual phase-locked loops, including one Frequency-modulated System integration unit lite (SIUL) Boot Assist Flash (BAF) supports factory programming using serial bootload through ‘Serial Boot Mode Protocol’. Physical Interface (PHY) can be: –UART –CAN Generic timer module (GTM122) – Intelligent complex timer module – 88 channels (24 input and 64 output) – 3 programmable fine grain multi-threaded cores – 26 KB of dedicated SRAM – Hardware support for engine control, motor control and safety related applications Enhanced analog-to-digital converter system with: – 5 separate 12-bit SAR analog converters – 2 separate 16-bit Sigma-Delta analog converters 5 Deserial Serial Peripheral Interface (DSPI) modules 5 LIN and UART communication interface (LINFlexD) modules 2 modular controller area network (M_CAN) modules, and one time-triggered controller area network (M_TTCAN). Dual-channel FlexRay controller Nexus development interface (NDI) per IEEE- ISTO 5001-2003 standard, with partial support for 2010 standard Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core logic Designed for eTQFP144 and eLQFP176 eTQFP144 (20 mm × 20 mm × 1.0 mm) Table 1. Device summary Memory Flash size Root Part Numbers Package eTQFP144 2624 KByte SPC574K72E5 2112 KByte SPC574K70E5 www.st.com |
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