SPC574K72E5 datasheet(39/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

Table 19 shows the VERY STRONG configuration output buffer electrical characteristics.

CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 14) are to be added to

calculate total signal capacitance (CTOT = CL + CIN).

Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.

Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0

Table 19. VERY STRONG configuration output buffer electrical characteristics(1)

Symbol

Parameter

Conditions(2)

Value(3)

Unit

Min

Typ

Max

ROH_V

PMOS output impedance



VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



IOH = 8 mA

——



CVDD_HV_IO = 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,



IOH = 7 mA

(4)

——

ROL_V

NMOS output impedance



VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



IOL = 8 mA

——



CVDD_HV_IO = 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,



IOL = 7 mA

(4)

——

fMAX_V

Output frequency



VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 25 pF

(5)

——

MHz

VDD_HV_IO = 3.3 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 15 pF

(4),(5)

——

tTR_V

10–90% threshold

transition time output pin

VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 25 pF

(5)

1—

5.3

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 50 pF

(5)

2.5

—

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 200 pF

(5)

—

tTR20-80

20–80% threshold

transition time(6) output pin

VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,



CL = 25 pF

(5)

0.8

—

VDD_HV_IO = 3.3 V ± 10%,

CL = 15 pF

(5)

1—5

tTRTTL

TTL threshold transition

time(7) for output pin in

VERY STRONG

configuration

VDD_HV_IO = 3.3 V ± 10%,

CL = 25 pF

(5)

1—5

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