SPC574K72E5 datasheet(86/127 Pages) STMICROELECTRONICS

tên linh kiện	SPC574K72E5

Giải thích chi tiết về linh kiện	32-bit Power Architecture based MCU for automotive applications

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Electrical characteristics

SPC574Kxx

86/127

DocID023601 Rev 5

3.17.1.4

Aurora debug port timing

Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is

guaranteed only after the startup time.

Table 46. Aurora debug port timing

Symbol

Characteristic

Value

Unit

Min

Max

1tREFCLK

Reference clock frequency

625

1250

MHz

tMCYC

Reference clock rise/fall time

—

400

2tRCDC

Reference clock duty cycle

3JRC

Reference clock jitter

—

4tSTABILITY

Reference clock stability

—

PPM

BER

Bit error rate

—

10–12

—

6JD

Transmit lane deterministic jitter

—

0.17

OUI

7JT

Transmit lane total jitter

—

0.35

OUI

8SO

Differential output skew

—

9SMO

Lane to lane output skew

—

1000

OUI

Aurora lane unit interval(1)

625 Mbps

1600

1.25 Gbps

800

± 100 PPM

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