SPC574K72E5 datasheet(16/127 Pages) STMICROELECTRONICS

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Package pinouts and signal descriptions

SPC574Kxx

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DocID023601 Rev 5

Package pinouts and signal descriptions

2.1

Package pinouts

The QFP and FusionQuad® package pinouts are shown in Figure 3 and Figure 4.

Figure 3. 144-pin QFP and 172-pin FQ configuration (top view)

PD[14]

PD[15]

PC[9]

PC[8]

PC[7]

PC[6]

PC[5]

PC[4]

PC[3]

NC/VDD_LV_BD5

PC[2]

PC[1]

PC[0]

PE[0]

PE[1]

PE[2]

PD[12]

PD[13]

PE[3]

PE[4]

PI[9]

VDD_LV

VDD_HV_IO_MAIN

VDD_HV_ADR_D

VSS_HV_ADR_D

PG[1]

PG[2]

PG[3]

PG[4]

PB[15]

PB[14]

PB[13]

PB[12]

PB[5]

PG[5]

PG[6]

PE[9]

PE[8]

PD[5]

PD[4]

PE[7]

PE[6]

PE[5]

PG[14]

PG[13]

VDD_LV

ESR0

PORST

PA[4]

PF[15]

TESTMODE

PF[14]

PA[6]

PA[5]

PA[9]

PA[7]

PA[8]

PA[14]

PD[6]

PD[7]

PF[13]

VDD_HV_IO_JTAG

XTAL

EXTAL

VSSOSC

VDD_LV

VDD_HV_IO_MAIN

PF[12]

PF[11]

PF[10]

PF[9]

PF[8]

108

107

106

105

104

103

102

101

100

eTQFP144 / FQ1723

Note:

Pins marked “NC” have no connection.

LVDS Test pins marked with an asterix (*) can be soldered to GND or left unconnected.

The eLQFP144 and FQ172 package pinouts are nearly identical, with the following exception:



A1–A28 are additional pins that appear only on the FQ172 package.

The shaded area in the middle of the pinout is an exposed pad that on both the eLQFP144 and FQ172 packages is the primary VSS

connection.

Pin 10 is NC in the 144-pin package and VDD_LV_BD in the 172-pin package.

VSS4

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