SPC574K72E5 datasheet(53/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

3.11.2

SAR ADC electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters

with full capacitive DAC. The SARn architecture allows input channel multiplexing.

For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.

Safety pull-down is available for port pin PB[5] and PE[14].

Table 28. SARn ADC electrical specification(1)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VALTREF

ADC alternate

reference voltage

VALTREF < VDD_HV_IO_MAIN

VALTREF < VDD_HV_ADV

4.5

5.5

C4.0

5.9

Extended range with reduce

TUE

VALTREF < VDD_HV_IO_MAIN

VALTREF < VDD_HV_ADV

2.0

5.9

VIN

ADC input signal

0 < VIN < VDD_HV_IO_MAIN

VSS_HV_ADR

VDD_HV_ADR

fADCK

Clock frequency

TJ < 150 °C

7.5

14.6

MHz

tADCPRECH

ADC precharge time

Fast SAR—fast precharge

135

—

Fast SAR—full precharge

270

—

Slow SAR (SARADC_B)—

fast precharge

270

—

Slow SAR (SARADC_B)—

full precharge

540

—

V

PRECH

ADC Precharge voltage Full precharge

VPRECH = VDD_HV_ADR/2

TJ < 150 °C

–0.25

0.25

Fast precharge

VPRECH = VDD_HV_ADR/2

TJ < 150 °C

–0.5

0.5

V

INTREF

Internal reference

voltage precision

Applies to all internal

reference points

(VSS_HV_ADR,

1/3 * VDD_HV_ADR,

2/3 * VDD_HV_ADR,

VDD_HV_ADR)

0.20

0.20

tADCSAMPLE SR

ADC sample time(2)

Fast SAR – 12-bit

configuration

0.750

—

µs

Slow SAR (SARADC_B) –

12-bit configuration

1.500

—

tADCEVAL

ADC evaluation time

12-bit configuration (25 clock

cycles)

1.712

—

µs

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