SPC574K72E5 datasheet(93/127 Pages) STMICROELECTRONICS

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DocID023601 Rev 5

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SPC574Kxx

Electrical characteristics

126

7tSUI

SIN setup time to

SCK



CPHA = 0(9)

SCK drive strength

Very strong

25 pF

25 –

(P(10) × tSYS

(5))

—ns

Strong

50 pF

31 –

(P(10) × tSYS

(5))

—

Medium

50 pF

52 –

(P(10) × tSYS

(5))

—

SIN setup time to

SCK



CPHA = 1(9)

SCK drive strength

Very strong

25 pF

25.0

—

Strong

50 pF

31.0

—

Medium

50 pF

52.0

—

SIN hold time

8tHI

SIN hold time from

SCK



CPHA = 0(9)

SCK drive strength

Very strong

0 pF

–

1 + (P(9) × tSYS

(4)

)

—ns

Strong

0 pF

–

1 + (P(9) × tSYS

(4)

)

—

Medium

0 pF

–

1 + (P(9) × tSYS

(4)

)

—

SIN hold time from

SCK



CPHA = 1(9)

SCK drive strength

Very strong

0 pF

–1.0

—

Strong

0 pF

–1.0

—

Medium

0 pF

–1.0

—

SOUT data valid time (after SCK edge)

9tSUO

SOUT data valid

time from SCK



CPHA = 0(10)

SOUT and SCK drive strength

Very strong

25 pF

—

7.0 + tSYS

(5)

Strong

50 pF

—

8.0 + tSYS

(5)

Medium

50 pF

—

16.0 + tSYS

(

SOUT data valid

time from SCK



CPHA = 1(10)

SOUT and SCK drive strength

Very strong

25 pF

—

7.0

Strong

50 pF

—

8.0

Medium

50 pF

—

16.0

Table 49. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0

or 1(1)(Continued)

Symbol

Characteristic

Condition

Value(2)

Unit

Pad drive(3)

Load (CL)Min

Max

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