SPC574K72E5 datasheet(84/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

Figure 25. Nexus event trigger and test clock timings

13(8)

tNTMSS

TMS/TMSC data setup time

—

tNTMSH

TMS/TMSC data hold time

—

15(9)

—

TDO/TDOC propagation delay from falling edge of TCK(10)

—16

—

TDO/TDOC hold time with respect to TCK falling edge (minimum

TDO/TDOC propagation delay)

2.25

—

Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O

section of the data sheet.

tCYC is system clock period.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less

than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency

being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number

greater than or equal to that specified here.

This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute

minimum TCK period specification.

This timing applies to TDI/TDIC, TDO/TDOC, TMS/TMSC pins; however, actual frequency is limited by pad type for

EXTEST instructions. Refer to pad specification for allowed transition frequency.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the

design (system frequency / 4) depending on the actual system frequency being used.

TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.

TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.

TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.

10. Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.

Table 44. Nexus debug port timing(1)(Continued)

Symbol

Characteristic

Value

Unit

Min

Max

TCK

EVTI

EVTO

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