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SPC574K72E5 bảng dữ liệu(PDF) 69 Page - STMicroelectronics |
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SPC574K72E5 bảng dữ liệu(HTML) 69 Page - STMicroelectronics |
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69 / 127 page ![]() DocID023601 Rev 5 69/127 SPC574Kxx Electrical characteristics 126 3.14 Aurora LVDS electrical characteristics The following table describes the Aurora LVDS electrical characteristics. Note: The Aurora interface is AC coupled, so there is no common-mode voltage specification. PN CC D Integrated phase noise (single side band) fRF_REF = 20 MHz — — –58 dBc DfRF_REF = 10 MHz — — –64 fVCO CC D PLL VCO frequency — — 640(2) —MHz tLOCK CC D PLL phase lock(3) —— — 40 µs PER REF SR T Input reference clock jitter (peak to peak) Single period, fRF_REF = 10 MHz —— 300 ps T Long term, fRF_REF = 10 MHz –500 — 500 ps PER EYE CC T Output Eye Jitter (peak to peak)(4) —— — 400 ps 1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO frequency is 624 MHz. PLL lock with 640 MHz VCO frequency guaranteed by production testing. 3. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device. 4. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See Figure 18. Table 34. LFAST PLL electrical characteristics(1)(Continued) Symbol C Parameter Conditions Value Unit Min Nominal Max Table 35. Aurora LVDS electrical characteristics(1)(2) Symbol C Parameter Conditions Value Unit Min Typ Max Transmitter FTX CC D Transmit Data Rate — — — 1.25 Gbps V OD_LVDS CC P Differential output voltage swing (terminated)(3) — 400 600 800 mV tTR_LVDS CC T Rise/Fall time (10%–90% of swing) — 60 — — ps RV_L_Tx SR D Differential Terminating resistance — 81 100 120 W TLoss CC D Transmission Line Loss due to loading effects —— — 6(4) dB Transmission line characteristics (PCB track) LLINE SR D Transmission line length — — — 20 cm ZLINE SR D Transmission line characteristic impedance —45 50 55 W Cac_clk SR D Clock Receive Pin External AC Coupling Capacitance Values are nominal, valid for +/– 50% tolerance 100 — 270 pF |
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