SPC574K72E5 datasheet(38/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

38/127

DocID023601 Rev 5

Table 18 shows the STRONG configuration output buffer electrical characteristics.

Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0

Table 18. STRONG configuration output buffer electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

ROH_S

PMOS output impedance

STRONG configuration

4.5 V < VDD_HV_IO < 5.5 V

Push pull, IOH < 8 mA

——



ROL_S

NMOS output impedance

STRONG configuration

4.5 V < VDD_HV_IO < 5.5 V

Push pull, IOL < 8 mA

——



fMAX_S

Output frequency



STRONG configuration

CL = 25 pF

(3)

——

MHz

CL = 50 pF

(4)

——

CL = 200 pF

(4)

——

tTR_S

Transition time output pin



STRONG configuration(4)

CL = 25 pF

4.5 V < VDD_HV_IO < 5.5 V

2.5

—

CL = 50 pF

4.5 V < VDD_HV_IO < 5.5 V

3.5

—

CL = 200 pF

4.5 V < VDD_HV_IO < 5.5 V

—

CL = 25 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

4—

CL = 50 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

6—

CL = 200 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

—

IDCMAX_S CC

Maximum DC current

—

t

SKEW_S

Difference between rise and

fall time

——

—

TPHL/PLH CC

Propagation delay

CL = 25 pF,

4.5 V < VDD_HV_IO < 5.9 V

—

CL = 25 pF,

3.0 V < VDD_HV_IO < 3.6 V

——

CL = 50 pF, 

4.5 V < VDD_HV_IO < 5.9 V

——

CL = 50 pF, 

3.0 V < VDD_HV_IO <

3.6 V(5)

——

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

All values need to be confirmed during device validation.

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