SPC574K72E5 datasheet(30/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

3.7

I/O pad specification

The following table describes the different pad type configurations.

Note:

Each I/O pin on the device supports specific drive configurations. See the signal description

table in the device reference manual for the available drive configurations for each I/O pin.

Typical application consumption, unloaded I/O with LVDS pins active and terminated.

Maximum VDD_LV consumption as for Section 3.15.2, Main voltage regulator electrical characteristics. Maximum junction

temperature including temperature due to power dissipation as for Section 4.5, Thermal characteristics.

Device in STOP mode running from the internal RCOSC, with the external oscillator and ADCs disabled. Includes regulator

consumption for VDD_LV generation. Includes static I/O current with no pins toggling. VDD_HV refers to all 5 V supplies

(VDD_HV_ADV, VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FLEX, and VDD_HV_PMC). The IDDAR current can be further

reduced by disabling the I/O pad compensation cells via the PDO bits in the ME_<mode>_MC registers in the mode entry

module (MC_ME).

Leakage of VDD_LV_BD at junction temperature of 150 °C with production device powered estimated at 120 mA

Aurora and LFAST enabled, further consumption of 70 mA on VDD_HV_IO_BD supply for Aurora transmission line

ISPIKE value is only valid for the use cases defined for the IDDAPP and IDDAPP_LV specifications and its conditions given in

Table 12 (DC electrical specifications).

Moving window, valid for IDDAPP and its conditions given in Table 12 (DC electrical specifications), with a maximum of

90 mA for the worst case application.

Condition 1: For power on period from 0 V up to normal operation with reset asserted.



Condition 2: From reset asserted until IRCOSC frequency.



Condition 3: Increasing frequency from IRCOSC to PLL full frequency.



Condition 4: reverse order for power down to 0 V.

10. Current variation is considered during boot or during shut-down sequence. Progressive clock switching should be use to

guarantee low current variation.This does not include current requested for the loading of the capacitances on the VDD_LV

domain. Please refer to Section 3.15.1, Power management integration, Iclamp specification

11. IDDOFF is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off

ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling the

clock ramp rates with the Progressive Clock Frequency Switching block on the device.

12. The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an

operating point within the specified voltage and temperature operating conditions.

Table 13. I/O pad specification descriptions

Pad type

Description

Weak configuration

Provides a good compromise between transition time and low electromagnetic emission.

Pad impedance is centered around 800



Medium configuration

Provides transition fast enough for the serial communication channels with controlled

current to reduce electromagnetic emission.

Pad impedance is centered around 200



Strong configuration

Provides fast transition speed; used for fast interface.

Pad impedance is centered around 50



Very strong configuration

Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of

rising/falling edge jitter.

Pad impedance is centered around 40



Differential configuration

A few pads provide differential capability providing very fast interface together with good

EMC performances.

Input only pads

These low input leakage pads are associated with the ADC channels.

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