| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
SPC574K72E5 bảng dữ liệu(PDF) 36 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC574K72E5 bảng dữ liệu(HTML) 36 Page - STMicroelectronics |
|
36 / 127 page ![]() Electrical characteristics SPC574Kxx 36/127 DocID023601 Rev 5 Table 17 shows the MEDIUM configuration output buffer electrical characteristics. Table 16. WEAK configuration output buffer electrical characteristics Symbol C Parameter Conditions(1) Value(2) Unit Min Typ Max ROH_W CC P PMOS output impedance weak configuration 4.5 V < VDD_HV_IO < 5.5 V Push pull, IOH < 0.5 mA — — 1040 ROL_W CC P NMOS output impedance weak configuration 4.5 V < VDD_HV_IO < 5.5 V Push pull, IOL < 0.5 mA — — 1040 fMAX_W CC T Output frequency weak configuration CL = 25 pF (3) —— 2 MHz CL = 50 pF (3) —— 1 DCL = 200 pF (3) —— 0.25 tTR_W CC T Transition time output pin weak configuration(4) CL = 25 pF, 4.5 V < VDD_HV_IO < 5.5 V 40 — 120 ns CL = 50 pF, 4.5 V < VDD_HV_IO < 5.5 V 80 — 240 DCL = 200 pF, 4.5 V < VDD_HV_IO < 5.5 V 320 — 820 CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V (5) 50 — 150 CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V (5) 100 — 300 CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V (5) 350 — 1050 t SKEW_W CC T Difference between rise and fall time —— — 25 % IDCMAX_W CC D Maximum DC current — — — 4 mA TPHL/PLH CC D Propagation delay CL = 25 pF, 4.5 V < VDD_HV_IO < 5.9 V —— 120 ns CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V —— 150 CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V —— 240 CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V (5) —— 300 1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid for VSIO[VSIO_xx] = 0 2. All values need to be confirmed during device validation. 3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 14) are to be added to calculate total signal capacitance (CTOT = CL + CIN). 4. Transition time maximum value is approximated by the following formula: 0 pF < CL < 50 pFtTR_W(ns) = 22 ns + CL(pF) 4.4 ns/pF 50 pF < CL < 200 pFtTR_W(ns) = 50 ns + CL(pF) 3.85 ns/pF 5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |