SPC574K72E5 datasheet(109/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

3.17.6

UART timing

UART channel frequency support is shown in the following table.

3.17.7

I2C timing

The I2C AC timing specifications are provided in the following tables.

Table 60. PSI5 timing

Symbol

Parameter

Value

Unit

Min

Max

tMSG_DLY

Delay from last bit of frame (CRC0) to assertion

of new message received interrupt

—3

µs

tSYNC_DLY

Delay from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin

—2

µs

tMSG_JIT

Delay jitter from last bit of frame (CRC0) to

assertion of new message received interrupt

—

cycles(1)

tSYNC_JIT

Delay jitter from internal sync pulse to sync

pulse trigger at the SDOUT_PSI5_n pin

—

±(1 PSI5_1µs_CLK +

1 PBRIDGEn_CLK)

cycles

Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

Table 61. UART frequency support

LINFlexD clock frequency

LIN_CLK (MHz)

Oversampling rate

Voting scheme

Max usable frequency

(Mbaud)

3:1 majority voting

810

Limited voting on one

sample with configurable

sampling point

13.33

516

420

100

3:1 majority voting

6.25

12.5

Limited voting on one

sample with configurable

sampling point

16.67

520

425

Table 62. I2C input timing specifications — SCL and SDA(1)

No.

Symbol

Parameter

Value

Unit

Min

Max

—

Start condition hold time

—

PER_CLK

Cycle(2)

—

Clock low time

—

PER_CLK Cycle

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