RM0352 datasheet(133/138 Pages) STMICROELECTRONICS

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RM0352

UART (universal asynchronous receive transmit)

137

12.6.13

Interrupt clear register, UARTICR

The UARTICR register is the interrupt clear register and is write-only. On a write of 1, the

corresponding interrupt is cleared. A write of 0 has no effect.

Table 130 lists the register bit

assignments.

12.6.14

Peripheral identification registers, UARTPeriphID0-3

The UARTPeriphID0-3 registers are four 8-bit registers, that span address locations

0xFE0 - 0xFEC. The registers can conceptually be treated as a 32-bit register. The read

only registers provide the following options of the peripheral:

PartNumber [11:0]

Identifies the peripheral. This is 0x011 for the UART.

Designer ID [19:12]

Identifies the designer. This is set to 0x41, to indicate that the ARM

designed the peripheral.

Revision [23:20]

The peripheral revision number is revision-dependent. See

Table 133: UARTPeriphID2 register. For the Brain device, r1p5

peripheral revision is used which corresponds to 0x3 value.

Configuration [31:24]

The configuration option of the peripheral. The configuration value

is 0.

Note:

When you design a systems memory map you must remember that the register has a 4 KB

memory footprint. All memory accesses to the peripheral identification registers must be

32-bit, using the LDR and STR instructions.

The four, 8-bit peripheral identification registers are described in the following subsections:

•

UARTPeriphID0 register

•

UARTPeriphID1 register

•

UARTPeriphID2 register

•

UARTPeriphID3 register

Table 130. UARTICR register

Bits

Name

Function

15:11

RESERVED

RESERVED, read as zero, do not modify.

OEIC

Overrun error interrupt clear. Clears the

UARTOEINTR interrupt.

BEIC

Break error interrupt clear. Clears the

UARTBEINTR interrupt.

PEIC

Parity error interrupt clear. Clears the

UARTPEINTR interrupt.

FEIC

Framing error interrupt clear. Clears the

UARTFEINTR interrupt.

RTIC

Receive timeout interrupt clear. Clears the

UARTRTINTR interrupt.

TXIC

Transmit interrupt clear. Clears the

UARTTXINTR interrupt.

RXIC

Receive interrupt clear. Clears the

UARTRXINTR interrupt.

3DSRMIC

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

2DCDMIC

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

1CTSMIC

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

RIMIC

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

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