RM0352 datasheet(74/138 Pages) STMICROELECTRONICS

74 / 138 page

I2C bus interface

RM0352

74/138

DocID024647 Rev 1

[25:20]

FREQ: internal clock frequency (SMBUS)

This field must be programmed to generate correct timings it is used to

generate 1 MHZ in internal clock frequency.

000000: not allowed

000001: not allowed

000010: i2c_clk = 2 MHz (kernel clock)

[19]

NACK: not-acknowledge enable (SMBUS)

In case of invalid data/command the software choose to cancel transfer by

setting this bit to '1' or to continue reception.

This bit is set and cleared by software and cleared by hardware when

I2C_CR: PE = 0.

0: no not-acknowledge returned

1: not-acknowledge returned after a next byte is received.

[18]

ENPEC: PEC enable (SMBUS)

This bit is used to enable or disable the PEC check /send.

0: PEC disabled

1: PEC enabled

[17]

ENARP: ARP enable (SMBUS)

0: ARP disable

1: ARP enable

SMBus Device default address recognized

[16]

SMBUS: SMBus mode

0: I

C mode

1: SMBus mode

[15]

FS: force stop enable bit, When set to 1b, the STOP condition is generated

0: force stop disabled

1: enable force stop

[14:13]

FON: Filtering on. FON sets the digital filters on the SDA, SCL line, according

to the I

C bus requirements, when standard open-drain pads are used:

00: no digital filters are inserted.

01: digital filters (filter 1 ck wide spikes) are inserted.

10: digital filters (filter 2 ck wide spikes) are inserted.

11: digital filters (filter 4 ck wide spikes) are inserted.

[12]

LM: loopback mode. LM sets the loopback operating mode for the I

controller: the Tx FIFO is internally redirect to the Rx FIFO. in order to trace

data stored in the Tx FIFO by reading it from the Rx FIFO.

0: normal mode.

1: loopback mode.

[11] RESERVED

[10] RESERVED

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