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RM0352 bảng dữ liệu(PDF) 53 Page - STMicroelectronics

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RM0352 bảng dữ liệu(HTML) 53 Page - STMicroelectronics

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RM0352
ARM© dual timer module (SP804)
137
Figure 9 shows how the timer clock enable is generated by the prescaler.
Figure 9. Prescale clock enable generation
Figure 10 shows an example of how the prescaler generates the timer clock enable for
a prescaler setting of divide by 16.
Figure 10. Example timing diagram of prescaler clock enable generation
Timer operation
After the initial application and release of PRESETn, the Timer state is initialized as follows:
•
The counter is disabled, TimerEn = 0
•
Free running mode is selected, TimerMode = 0 and OneShot = 0
•
16-bit counter mode is selected, TimerSize = 0
•
Prescalers are set to divide by 1, TimerPre = 0x0
•
Interrupts are cleared but enabled, IntEnable = 1
•
The load register is set to zero
•
The counter value is set to 0xFFFFFFFF.
The operation in each of the three Timer modes is described in:
•
Free running mode
•
Periodic mode
•
One-shot mode



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