RM0352 datasheet(84/138 Pages) STMICROELECTRONICS

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I2C bus interface

RM0352

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DocID024647 Rev 1

10.2.7

I2C transmit FIFO threshold register (I2C_TFTR)

Table 77. I2C transmit FIFO threshold register (I2C_TFTR)

10.2.8

I2C receive FIFO threshold register (I2C_RFTR)

Table 78. I2C receive FIFO threshold register (I2C_RFTR)

Address:

I2CBaseAddress + 0x20

Type:

R/W

Reset:

0x00000000

Description:

C receive FIFO threshold register

I2C transmit FIFO threshold register (I2C_TFTR)

18 17 16

RESERVED

THRESHOLD_TX

RR/W

Address:

I2CBaseAddress + 0x1C

Type:

R/W

Reset:

0x00000000

Description: I

transmit FIFO threshold register

[9:0]

THRESHOLD_TX: threshold Tx. THRESHOLD_TX contains the threshold

value, in terms of number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal than the threshold

value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading

of data to the application (in CPU mode).

I2C receive FIFO threshold register (I2C_RFTR)

31 30 29 28 27

25 24

RESERVED

THRESHOLD_RX

RR/W

[9:0]

THRESHOLD_RX: threshold Rx. THRESHOLD_RX contains the threshold

value, in terms of number of bytes, of the Rx FIFO.

When the number of entries of the Rx FIFO is greater or equal than the

threshold value, the interrupt bit I2C_RISR:RXFNF is set in order to request

the download of received data to the application. The application (in CPU

mode) shall download the received data based on threshold

(I2C_RISR:RXFNF).

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