RM0352 datasheet(51/138 Pages) STMICROELECTRONICS

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RM0352

ARM© dual timer module (SP804)

137

Free running counter blocks

The two FRCs are identical and contain the 32/16-bit down counter and interrupt

functionality. The counter logic is clocked independently of PCLK by TIMCLK in conjunction

with a clock enable TIMCLKENX although there are constraints on the relationship between

PCLK and TIMCLK. See

Section : Clock signals and clock enables on page 51 for details of

these constraints.

Although the two FRCs are driven from a common clock, TIMCLK, each timer count rate

can be independently controlled by their respective clock enables, TIMCLKEN1 and

TIMCLKEN2. The prescaler in each FRC gives a further independent control of the count

rate of each FRC. See

Section : Timer operation on page 53 or an operational description of

the FRCs.

Interface reset

The dual timer module is reset by the global reset signal PRESETn.

The values of the registers after reset are described in

Section 8.3: Programmer's model on

page 57. In summary, the Timer is initialized to the following state after reset:

•

The counter is disabled

•

Free running mode is selected

•

16-bit counter mode is selected

•

Prescalers are set to divide by 1

•

Interrupts are cleared but enabled

•

The load register is set to zero

•

The counter value is set to 0xFFFFFFFF.

Clock signals and clock enables

The dual timer module uses two input clocks:

•

PCLK is used to time all APB accesses to the dual timer module registers.

•

TIMCLK is qualified by the clock enables, TIMCLKEN1 and TIMCLKEN2 (tied high for

Brain device), and used to clock the prescalers, counters and their associated interrupt

logic. This qualified TIMCLK rate is referred to as the effective timer clock rate. The

prescaler counter only decrements on a rising edge of TIMCLK when TIMCLKENX is

HIGH. The Timer counter only decrements on a rising edge of TIMCLK when

TIMCLKENX is HIGH and the prescaler counter generates an enable (see

Section :

Prescaler operation on page 52.

The relationship between TIMCLK and PCLK must observe the following constraints:

•

The rising edges of TIMCLK must be synchronous and balanced with a rising edge of

PCLK

•

TIMCLK frequency cannot be greater than PCLK frequency.

TIMCLK, TIMCLKEN1, and TIMCLKEN2 are used in the ways described in the following

sections:

•

TIMCLK equals PCLK and TIMCLKENX equals one for dual timers 3 to 0.

•

TIMCLK is less than PCLK and TIMCLKENX equals one for dual timers 7 to 4.

Note:

Unless otherwise stated these examples use a prescale setting of divide by 1. The

examples apply to either Timer1 or Timer2 in the module. TIMCLKENX refers to either

TIMCLKEN1 or TIMCLKEN2.

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