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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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RM0352 bảng dữ liệu(PDF) 58 Page - STMicroelectronics |
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RM0352 bảng dữ liệu(HTML) 58 Page - STMicroelectronics |
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58 / 138 page  ARM© dual timer module (SP804) RM0352 58/138 DocID024647 Rev 1 8.3.1 Summary of registers A summary of the registers is provided in Table 52 and base address of each dual timer is listed below. The Timer0 base address is 0xA640_0000 The Timer1 base address is 0xA740_0000. The Timer2 base address is 0xA840_0000. The Timer3 base address is 0xA940_0000. The Timer4 base address is 0xA680_0000. The Timer5 base address is 0xA780_0000. The Timer6 base address is 0xA880_0000. The Timer7 base address is 0xA980_0000. Table 52. Summary of registers Address Type Width Reset value Name Description Base+0x00 Read/write 32 0x00000000 Timer1Load See Section : Load register, TimerXLoad on page 60 Base+0x04 Read 32 0xFFFFFFFF Timer1Value See Section : Current value register, TimerXValue on page 60 Base+0x08 Read/write 8 0x20 Timer1Control See Section : Control register, TimerXControl on page 61 Base+0x0C Write - - Timer1IntClr See Section : Interrupt clear register. TimerXIntClr on page 61 Base+0x10 Read 1 0x0 Timer1RIS See Section : Raw interrupt status register, TimerXRIS on page 62 Base+0x14 Read 1 0x0 Timer1MIS See Section : Masked interrupt status register, TimerXMIS on page 62 Base+0x18 Read/write 32 0x00000000 Timer1BGLoad See Section : Background load register, TimerXBGLoad on page 62 Base+0x20 Read/write 32 0x00000000 Timer2Load See Section : Load register, TimerXLoad on page 60 Base+0x24 Read 32 0xFFFFFFFF Timer2Value See Section : Current value register, TimerXValue on page 60 Base+0x28 Read/write 8 0x20 Timer2Control See Section : Control register, TimerXControl on page 61 Base+0x2C Write - - Timer2IntClr See Section : Interrupt clear register. TimerXIntClr on page 61 Base+0x30 Read 1 0x0 Timer2RIS See Section : Raw interrupt status register, TimerXRIS on page 62 Base+0x34 Read 1 0x0 Timer2MIS See Section : Masked interrupt status register, TimerXMIS on page 62 |
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