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RM0352 bảng dữ liệu(PDF) 83 Page - STMicroelectronics

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RM0352
I2C bus interface
137
10.2.6
I2C receive FIFO register (I2C_RFR)
Table 76. I2C receive FIFO register (I2C_RFR)
Address:
I2CBaseAddress + 0x18
Type:
R
Reset:
0x00000000
I2C receive FIFO register (I2C_RFR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18 17 16
15
14 13 12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
RDATA
R
R
Description: I
2
C receive FIFO register
[7:0]
RDATA: receive data. RDATA contains the received payload, related to
a master read or write-to-slave operation, to be read from the Rx FIFO. The
RDATA(0) is the first LSB bit received over the I
2
C line. In case the FIFO is
full, the I
2
C controller stretches automatically the I
2
C clock line until a new
entry is available. For a write-to-slave operation, when the slave is addressed,
the interrupt I2C_RISR:WTSR bit is asserted for notification to the CPU. In
CPU mode the FIFO management shall be based on the assertion of the
interrupt bit I2C_RISR:RXFNF, related to the nearly-full threshold.



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