RM0352 datasheet(132/138 Pages) STMICROELECTRONICS

132 / 138 page

UART (universal asynchronous receive transmit)

RM0352

132/138

DocID024647 Rev 1

12.6.12

Masked interrupt status register, UARTMIS

The UARTMIS register is the masked interrupt status register. It is a read-only register. This

no effect.

All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when

reset. The modem status interrupt bits are undefined after reset.

Table 129 lists the register

bit assignments.

Table 129. UARTMIS register

Bits

Name

Function

15:11

RESERVED, read as zero, do not modify.

OEMIS

Overrun error masked interrupt status. Returns the masked interrupt state of the

UARTOEINTR interrupt.

BEMIS

Break error masked interrupt status. Returns the masked interrupt state of the

UARTBEINTR

interrupt.

PEMIS

Parity error masked interrupt status. Returns the masked interrupt state of the

UARTPEINTR

interrupt.

FEMIS

Framing error masked interrupt status. Returns the masked interrupt state of the

UARTFEINTR interrupt.

RTMIS

Receive timeout masked interrupt status. Returns the masked interrupt state of the

UARTRTINTR interrupt.

TXMIS

Transmit masked interrupt status. Returns the masked interrupt state of the

UARTTXINTR

interrupt.

RXMIS

Receive masked interrupt status. Returns the masked interrupt state of the

UARTRXINTR

interrupt.

DSRMMIS

nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the

UARTDSRINTR interrupt.

DCDMMIS

nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the

UARTDCDINTR interrupt.

1CTSMMIS

nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the

UARTCTSINTR interrupt.

0RIMMIS

nUARTRI modem masked interrupt status. Returns the masked interrupt state of the

UARTRIINTR interrupt.

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