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XM33C321ASPZR bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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XM33C321ASPZR bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 122 page  6.2 Pin Attributes The following table describes the function available on every pin for each device package. Note Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. The IOMUX only supports connecting one IOMUX-managed digital function to the pin at the same time. The PINCM.PF and PINCM.PC in IOMUX are recommended to be set to 0 when non-IOMUX managed functions (such as analog connections) are intended to be used on a pin. However, non-IOMUX managed signals (such as analog inputs and WAKE inputs) can be enabled on a pin at the same time that an IOMUX managed digital function is enabled on the pin, provided there is no contention between the functions. In this case, the designer must verify that no contention exists between the functions enabled on each pin. Table 6-1. Digital IO Features by IO Type BUFFER TYPE INVERSION CONTROL DRIVE STRENGTH CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC SDIO (standard drive) Y Y Y SDIO (standard drive) with wake Y Y Y Y HDIO (High drive) Y Y Y Y Y HSIO (High speed) Y Y Y Y Table 6-2. Pin Attributes (PFA, PZ, PN, PM, RGZ, ZAW, YSG Packages) PFA PIN PZ PIN PN PIN PM PIN RGZ PIN ZAW PIN YSG PIN PIN NAME/ IOMUX REG/ IOMUX ADDR SIGNAL NAME IOMUX NAME SIGNAL TYPE BUFFER TYPE 6 6 6 38 4 B4 F6 NRST WAKE (Non-IOMUX 1) 0 I RESET NRST (Non-IOMUX 2) 0 RESET 1 1 1 33 1 D3 C7 PA0 PINCM1 0x400cc000 PA0 1 IO SDIO (standard )with wake TIMA0_0_FAL1 2 I UC1_0_SDA_TX 3 IOD UC13_3_SCLK_S CL_RX 4 IOD UC12_TX 5 O UC15_0_SDA 6 IOD WAKE (Non-IOMUX 1) 0 I BSL_I2C_SDA (Non-IOMUX 2) 0 IOD 2 2 2 34 2 C4 D6 PA1 PINCM2 0x400cc004 PA1 1 IO SDIO (standard )with wake TIMA0_1_FAL0 2 I UC1_0_SCL_RX 3 IOD UC13_3_PICO_S DA_TX 4 IOD UC12_RX 5 I UC15_0_SCL 6 IOD TIMG8_0_IDX 7 I TIMA0_0_C1 8 IO WAKE (Non-IOMUX 1) 0 I BSL_I2C_SCL (Non-IOMUX 2) 0 IOD www.ti.com MSPM33C321A, MSPM33C3219 SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: MSPM33C321A MSPM33C3219 |
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