XM33C321ASPZR datasheet(4/122 Pages) TI2

4 / 122 page

4 Functional Block Diagram

Power Domain

PD1

CPU SUB SYSTEM

Arm® Cortex®-M33

fCPU = 160 MHz

TrustZone®+ SAU +

IDAU

NVIC

FPU

DSP

SWD

DMA0

4 channels

DMA1

12 channels

ROM

(Root of Trust, Boot Loader)

4 kB

Cache

Flash with ECC

Up to 2 x 512 kB

1 x 32 kB

Data Flash

SRAM with ECC

3 x 64 kB (192 kB) Non-Reten on

SRAM with ECC

1 x 64 kB (64 kB) Reten on

UNICOMM13_1

(UART/I2C/SPI)

UNICOMM14

(UART+LIN/I2C)

VDD

Voltage Domain

C-AHB

S-AHB

UNICOMM12

(UART)

UNICOMM13_0

(UART/I2C/SPI)

UNICOMM15_0

(I2C+SMBus)

UNICOMM15_1

(I2C+SMBus)

UNICOMM2

(SPI)

UNICOMM13_3

(UART/I2C/SPI)

UNICOMM13_2

(UART/I2C/SPI)

HSADC0 12-bit

9.4 MSPS 21-channels

HSADC1 12-bit

9.4 MSPS 15-channels

TIMA0_0

TIMA0_1

QSPI

TIMG12_0

SHA-256-HMAC

AES-256

KeyStore

PKA

(ECDSA/ECDH)

I2S 0

I2S 1

CAN-FD 0

CAN-FD 1

TIMG4_2

TIMG4_3

TIMG8_0

TIMG8_1

CRC

DMA0 Con g

DMA1 Con g

Flash Con g

SRAM Con g

EAM

PD1 MCLK Clock Domain

PD1 MCLK/2 Clock Domain

PD1 MCLK/4 Clock Domain

Memory and

PeripheralFirewall (GSC)

PD0 MCLK/4 Clock Domain

Power Domain

PD0

TRNG

IOMUX

Flash Controller

PMU (SYSCTL)

UNICOMM1_0

(UART+LIN/I2C)

UNICOMM1_1

(UART+LIN/I2C)

COMPARATOR 0

COMPARATOR 1

TIMG4_0

TIMG4_1

DEBUGSS

WWDT

GPIO

Global Security

Control (GSC)

Figure 4-1. MSPM33C321x Functional Block Diagram

MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

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