XM33C321ASPZR datasheet(86/122 Pages) TI2

86 / 122 page

For more details, see the I2C (UNICOMM) chapter of the MSPM33C3x 160-MHz Microcontrollers Technical

Reference Manual.

8.14.1.3 SPI (UNICOMM)

The serial peripheral interface (SPI) peripherals function support the following key features:

• Supports up to 40 Mbits/s in controller mode 1

• Configurable as a controller or a peripheral

• Support for up to 4 chip select for both controller and peripheral

• Supports single parity for transmit and receive

• Programmable clock prescaler and bit rate

• Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode)

• Supports TI mode, Motorola mode and National Microwire format

• See Table 8-16 for detailed information on supported features

Table 8-16. SPI (UNICOMM) Features

Supported Features

UC2.SPI

UC13.SPI

Controller and Peripheral mode

Yes

Supports Parity function

Yes

Supports Repeat mode transfer

Yes

Supports Receive timeout

Yes

Supports Command/Data control

Yes

Supports 4 chip selects

Yes

For more details, see the SPI (UNICOMM) chapter of the MSPM33C3x 160-MHz Microcontrollers Technical

Reference Manual.

8.14.2 CAN-FD

The controller area network (CAN) controller enables communication with a CAN2.0A, CAN2.0B, or CAN-FD bus

and is compliant to ISO 11898-1:2015 standard supporting up to 5Mbit/s bit rate. Key features of the CAN-FD

peripheral include:

• Full support for 64-byte CAN-FD frames

• Dedicated 1KB message SRAM with ECC

• Configurable transmit FIFO, transmit queue and event FIFO (up to 32 elements)

• Up to 32 dedicated transmit buffers and 64 dedicated receive buffers

• Two configurable receive FIFOs (up to 64 elements each)

• Up to 128 filter elements

• Two interrupt lines

• Power-down and wake-up support

• Timestamp counter

For more details, see the CAN-FD chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference

Manual.

8.14.3 Quad SPI (QSPI)

The Quad SPI (QSPI) controller interfaces to an external serial flash memory over 4 data lines to provide fast

data transfer up to 20Mbytes/s.

• Supports single, bi (dual) and quad data operations for data communication up to 40MHz serial clock

• Programmable interface supports QSPI operation in both Mode-0 and Mode-3

• Supports both 3-byte and 4-byte address external QSPI flash memory

• Preconfigured read frame formats and dummy clock insertion for optimized read operations

1 Only SPI signals on HSIO pins support data rates up to 40 Mbits/s; see the Pin Diagrams section for HSIO pins.

MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

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