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XM33C321ASPZR bảng dữ liệu(PDF) 46 Page - Texas Instruments

tên linh kiện XM33C321ASPZR
Giải thích chi tiết về linh kiện  MSPM33C321x Mixed-Signal Microcontrollers
PDF  122 Pages
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XM33C321ASPZR bảng dữ liệu(HTML) 46 Page - Texas Instruments

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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tERASE (SEC)
Sector erase time
<10k erase/program cycles
20
200
ms
tERASE (BANK)
Bank erase time
<10k erase/program cycles
22
220
ms
(1)
Data flash with high erase/program cycle endurance can be used for EEPROM emulation.
(2)
Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is
considered to be one erase operation.
(3)
Maximum number of write operations allowed per word line (256 bytes) before the word line must be erased. If additional writes to the
same word line are required, a sector erase is required once the maximum number of write operations per word line is reached.
(4)
Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in
the flash controller.
(5)
Sector program time is defined as the time from when the first word program command is triggered until the final word program
command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each
flash word (after the first flash word) into the flash controller during programming of the sector.
(6)
Flash word size is 128 data bits (16 bytes). On devices with ECC, the total flash word size is 144 bits (128 data bits plus 16 ECC bits).
7.7 Power Supply Sequencing
7.7.1 Power Supply Ramp
Figure 7-1 shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown.
POR
BOR
Running
Running
BOR
POR BOR
Running
POR-
POR+
BOR0-
BOR0+
No reset
asserted
BOR
asserted
POR
asserted
BOR
released
POR
released
POR
released
BOR
released
Time (t)
POR/BOR levels are met
for specified |dVDD/dt|
BOR
released
Figure 7-1. Power Cycle POR and BOR Conditions
7.7.2 POR and BOR
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
Power supply range
1.71
3.6
V
dVDD/dt
VDD (supply voltage) slew rate
Rising
0.1
V/µs
Falling (1)
0.01
Falling, STANDBY
0.1
V/ms
VPOR+
Power-on reset voltage level
Rising
0.95
1.30
1.59
V
VPOR-
Falling
0.9
1.25
1.53
VHYS, POR
POR hysteresis
30
58
74
mV
VBOR0+,
COLD
Brown-out reset voltage level 0 (default level)
Cold start, rising
1.5
1.6
1.7
V
VBOR0+
Rising (1)
1.625
1.66
1.695
VBOR0-
Falling (1)
1.61
1.645
1.68
VBOR0, STBY
STANDBY mode
1.54
1.625
1.69
MSPM33C321A, MSPM33C3219
SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026
www.ti.com
46
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: MSPM33C321A MSPM33C3219



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