XM33C321ASPZR datasheet(63/122 Pages) TI2

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8 Detailed Description

The following sections describe all of the components that make up the devices in this data sheet. The

peripherals integrated into these devices are configured by software through Memory Mapped Registers

(MMRs). For more details, see the corresponding chapter of the MSPM33C3 Series 160-MHz Microcontrollers

Technical Reference Manual.

8.1 Arm Cortex-M33 core with TrustZone and FPU

The Arm Cortex-M33 is a high performance low-power 32-bit CPU, delivering efficient security to embedded

applications. The 160MHz CPU sub system (MCPUSS) implements an Arm Cortex-M33 CPU with TrustZone

technology, FPU, DSP extensions and includes a 4kB instruction cache, a system timer (SYSTICK), a memory

protection unit, and interrupt management features. Key features of the MCPUSS:

• Arm TrusztZone technology, using Armv8-M extension supporting secure and non-secure states

• Floating point unit (FPU) with support for IEEE 754 single precision floating point operations

• Digital signal processing (DSP) extension

• 4kB instruction cache with 0-wait state exectution at 160 MHz

• Configurable memory protection unit (MPU), supporting up to 16 regions for secure and non-secure

applications

• Configurable secure attribution unit (SAU) with up to 8 regions as secure or non secure

• System timer (SysTick) with 24-bit down counter and automatic reload

• Nested vectored interrupt controller (NVIC) with 64 programmable priority levels

• Micro-trace buffer (MTB) capable of storing 4 of the previous CPU branch addresses

• Full debug capabilities with support 4 data watchpoints and 8 breakpoint comparators

8.2 Power Management and Clock Unit (PMCU)

8.2.1 Power Management Unit (PMU)

The power management unit (PMU) generates the internally regulated core supplies for the device and provides

supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the

PMU itself as well as analog peripherals. Key features of the PMU include:

• Power-on reset (POR) supply monitor

• Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds

• Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance

performance with power consumption

• Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management

trim is corrupted

For more details, see the PMU chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference

Manual.

8.2.2 Clock Module (CKM)

The clock module provides the following oscillators:

• LFOSC: Internal low-frequency oscillator (32 kHz)

• SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim)

• LFXT/LFCKIN : Low-frequency external crystal oscillator or digital clock input (32 kHz)

• HFXT/HFCKIN: High-frequency external crystal oscillator or digital clock input (4 to 48 MHz)

• SYSPLL: System phase locked loop with 1 output (5 to 160 MHz)

The following clocks are distributed by the clock module for use by the processor, bus, and peripherals:

• MCLK: Main system clock for PD1 peripherals in MCLK domain, derived from SYSOSC, or HSCLK, active in

RUN and SLEEP modes

• MCLK/2: Main system clock for PD1 peripherals in MCLK/2 domain, derived MCLK and divided by 2

• MCLK/4: Main system clock for PD1 peripherals in MCLK/4 domain, derived MCLK and divided by 4

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MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

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