XM33C321ASPZR datasheet(72/122 Pages) TI2

72 / 122 page

Table 8-4. Interrupt Vector Number (continued)

PERIPHERAL NAME

NVIC IRQ

LFSS

DMA0

DMA1

I2S0

I2S1

QSPI0

SHA256

PKA

UNICOMM13_1

UNICOMM13_2

UNICOMM13_3

8.5 Embedded Flash Memory

A dual bank of non-volatile flash memory (up to 1MB/512kB total) and a separate data flash bank (32kB) is

provided for storing executable program code and application data.

Key features of the flash include:

• Hardware ECC protection (encode and decode) with single bit error correction and double-bit error detection.

• In-circuit program and erase operations supported across the entire recommended supply range.

• Read while write operation supported in dual bank mode.

• Small 2kB sector sizes (minimum erase resolution of 2kB)

• Flash write/erase protection

– First 32 sectors of each flash bank has write/erase protection with a granularity of 2kB.

– Remaining sectors of each flash bank write/erase protection with a granularity of 16kB.

• Trustzone security and MPU protections extended for all initiators using Global Security Controller (GSC)

Refer to the NVM chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference Manual.

8.6 Embedded SRAM

The device includes a 256kB of SRAM across four banks fully protected by error correction code (ECC). SRAM

memory can be used for storing volatile information such as the call stack, heap, global data, and code.

• Hardware ECC protection (encode and decode) with single bit error correction and double-bit error detection.

• SRAM0 (64kB) memory fully retained in low power modes of STOP and STANDBY operating mode.

• Trustzone security and MPU protections extended for all initiators using Global Security Controller (GSC).

– 16-kB SRAM chunk size with variable size for ease of memory allocation for secure/non-secure and

privilege/user mode threads.

• Automatic zeroisation of memory contents at power up.

• No arbitrated access to initiators accessing different memory bank simultaneously.

• Interleaved access between SRAM banks 2 and 3.

• 4-deep SRAM cache buffer for read and write operations for improved access time for same bank access

The Table 8-5 describes the operational conditions for the multiple SRAM banks on the device.

Table 8-5. SRAM Bank Property

SRAM0

SRAM1/2/3

0-Wait State Frequency

90MHz

120MHz

RUN Mode State

ACTIVE

SLEEP Mode State

ACTIVE

STOP Mode State

RETAINED

OFF

MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

www.ti.com

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