XM33C321ASPZR datasheet(64/122 Pages) TI2

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• CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode

• ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes

• MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes. This

clock can be used only by peripherals in the PD0 clock domain.

• LFCLK: 32-kHz fixed low-frequency clock for peripherals or ULPCLK, active in RUN, SLEEP, STOP, and

STANDBY modes. This clock can be used only by peripherals in the PD0 clock domain.

• CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes

• HFCLK: High-frequency clock derived from HFXT or HFCLK_IN, available in RUN and SLEEP mode

• HSCLK: High-speed clock derived from HFCLK or the SYSPLL, available in RUN and SLEEP mode

• CANCLK: CAN functional clock, derived from HFCLK or SYSPLL

• I2SCLK: I2SCLK functional clock, derived from HFCLK or SYSPLL

• LFOSCCLK: Used for IWDT & WWDT, derived from LFOSC

For more details, see the CKM chapter of the MSPM33 C3-Series 160-MHz Microcontrollers Technical

Reference Manual.

8.2.3 Operating Modes

MSPM33C3x MCUs provide five main operating modes (power modes) to allow for optimization of the device

power consumption based on application requirements. In order of decreasing power, the modes are: RUN,

SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code when in RUN mode. Peripheral

interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN

mode completely disables the internal core regulator to minimize power consumption, and wake is only possible

via NRST, SWD interface, a logic level match on certain IOs, or an interrupt from the low frequency sub system

(LFSS).

To further balance performance and power consumption, MSPM33C3x devices implement three power domains:

PD1, PD0, VBAT. PD1 contains the CPU, memories, and high performance peripherals. PD1 contains is always

powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 contains low speed, low power

peripherals which are always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both

disabled in SHUTDOWN mode. VBAT can be powered by a separate power source other than Vdd or can be

externally connected to Vdd. VBAT power domain contains the low frequency sub system and is always active

when power is applied.

8.2.3.1 Functionality by Operating Mode

Supported functionality in each operating mode is given in Table 8-1.

Functional key:

• EN: The function is enabled in the specified mode.

• DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's

configuration is retained.

• OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.

• NS: The function is not automatically disabled in the specified mode, but it is not supported.

• OFF: The function is fully powered off in the specified mode, and no configuration information is retained.

When waking up from an OFF state, all module registers must be re-configured to the desired settings by

application software.

Table 8-1. Supported Functionality by Operating Modes

OPERATING MODE

RUN

SLEEP

STOP

STANDBY

SHUTDOWN

Oscillators

SYSOSC

DIS

OFF

LFOSC or LFXT

EN (LFOSC or LFXT)

HFXT

OPT

DIS

OFF

SYSPLL

OPT

DIS

OFF

MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

www.ti.com

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