IMX93CEC datasheet(122/123 Pages) NXP

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Contents

i.MX 93 introduction............................................2

1.1

Ordering information...........................................6

Block diagram.....................................................9

Special signal considerations........................... 10

3.1

Unused input and output guidance...................11

Electrical characteristics...................................12

4.1

Chip-level conditions........................................ 13

4.1.1

Absolute maximum ratings............................... 13

4.1.2

Thermal resistance...........................................14

4.1.3

Power architecture........................................... 15

4.1.4

Operating ranges..............................................18

4.1.5

Maximum frequency of main modules..............19

4.1.6

Clock sources...................................................19

4.1.7

Maximum supply currents................................ 21

4.2

Power modes................................................... 22

4.2.1

Power mode definition......................................22

4.2.2

Low power modes............................................ 23

4.2.3

Chip power in different Low Power modes.......24

4.3

Power supplies requirements and restrictions..25

4.3.1

Power-up sequence......................................... 26

4.3.2

Power-down sequence.....................................26

4.4

PLL electrical characteristics............................27

4.5

I/O DC parameters........................................... 27

4.5.1

General purpose I/O (GPIO) DC parameters... 27

4.5.2

DDR I/O DC electrical characteristics.............. 28

4.5.3

LVDS DC parameters.......................................28

4.6

I/O AC parameters........................................... 29

4.6.1

General purpose I/O (GPIO) AC parameters... 30

4.6.2

DDR I/O AC electrical characteristics...............31

4.6.3

LVDS AC Parameters...................................... 32

4.7

Differential I/O output buffer impedance...........33

4.7.1

DDR I/O output impedance.............................. 33

4.8

System modules timing.................................... 33

4.8.1

Reset timing parameters.................................. 33

4.8.2

WDOG Reset timing parameters......................33

4.8.3

JTAG timing parameters.................................. 34

4.8.4

SWD timing parameters................................... 35

4.8.5

DDR SDRAM–specific parameters (LPDDR4/

LPDDR4X)........................................................36

4.9

Display and graphics........................................ 37

4.9.1

MIPI D-PHY electrical characteristics...............37

4.9.2

LCD Controller (LCDIF) timing parameters...... 40

4.10

Audio................................................................ 41

4.10.1

SAI switching specifications............................. 41

4.10.2

SPDIF timing parameters................................. 44

4.10.3

PDM Microphone interface timing parameters 45

4.10.4

Medium Quality Sound (MQS) electrical

specifications....................................................46

4.11

Analog.............................................................. 46

4.11.1

12-bit ADC electrical specifications.................. 46

4.11.2

12-bit ADC input impedance equivalent circuit

diagram............................................................ 48

4.12

External peripheral interface parameters......... 49

4.12.1

Ultra-high-speed SD/SDIO/MMC host interface

(uSDHC) AC timing.......................................... 49

4.12.2

Ethernet controller (ENET) AC electrical

specifications....................................................57

4.12.3

Ethernet Quality-of-Service (QOS) electrical

specifications....................................................60

4.12.4

LPSPI timing parameters................................. 64

4.12.5

LPI2C timing parameters..................................67

4.12.6

Improved Inter-Integrated Circuit Interface (I3C)

specifications....................................................68

4.12.7

CAN network AC electrical specifications........ 70

4.12.8

Timer/Pulse width modulator (TPM) timing

parameters....................................................... 70

4.12.9

FlexSPI timing parameters............................... 71

4.12.10

LPUART I/O configuration and timing parameters

......................................................................... 78

4.12.11

Flexible I/O controller (FlexIO) electrical

specifications....................................................78

4.12.12

USB PHY parameters...................................... 78

Boot mode configuration.................................. 79

5.1

Boot mode configuration pins...........................79

5.2

Boot device interface allocation........................80

Package information and contact assignments83

6.1

11 x 11 mm package information..................... 83

6.1.1

11 x 11 mm, 0.5 mm pitch, ball matrix..............83

6.1.2

11 x 11 mm supplies contact assignments and

functional contact assignments........................ 85

6.1.3

11 x 11 mm, 0.5 mm pitch, ball map................ 95

6.2

9 x 9 mm package information....................... 100

6.2.1

9 x 9 mm, 0.5 mm pitch, ball matrix................100

6.2.2

9 x 9 mm supplies contact assignments and

functional contact assignments...................... 102

6.2.3

9 x 9 mm, 0.5 mm pitch, ball map.................. 109

6.3

DDR pin function list.......................................113

Revision history.............................................. 114

Legal information............................................119

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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