IMX93CEC datasheet(40/123 Pages) NXP

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[7] This value represents a corner point in a piecewise linear curve.

4.9.1.4 MIPI LP-RX specifications

Table 41. MIPI low power receiver DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

VIH

Logic 1 input voltage

740

—

VIL

Logic 0 input voltage, not in ULP state

—

550

VIL-ULPS

Logic 0 input voltage, ULP state

—

300

VHYST

Input hysteresis

—

Table 42. MIPI low power receiver AC specifications

Symbol

Parameter

Min

Typ

Max

Unit

eSPIKE[1],[2]

Input pulse rejection

—

300

V.ps

TMIN-RX[3]

Minimum pulse width response

—

VINT

Peak Interference amplitude

—

200

fINT

Interference frequency

450

—

MHz

[1] Time-voltage integration of a spike above VIL when in LP-0 state or below VIH when in LP-1 state.

[2] An impulse below this value will not change the receiver state.

[3] An input pulse greater than this value shall toggle the output.

4.9.1.5 MIPI LP-CD specifications

Table 43. MIPI contention detector DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

VIHCD

Logic 1 contention threshold

450

—

VILCD

Logic 0 contention threshold

—

200

4.9.2 LCD Controller (LCDIF) timing parameters

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

Figure 14 shows the LCDIF timing and Table 44 lists the timing parameters.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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