IMX93CEC datasheet(44/123 Pages) NXP

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S15

S13

S15

S17

S18

S15

S16

S14

S16

S11

S12

SAI_BCLK (input)

SAI_FS (output)

SAI_TXD

SAI_RXD

SAI_FS (input)

S19

Figure 16. SAI Timing — Target Mode

4.10.2 SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF

data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 48 and Figure 17 and Figure 18 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF),

including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock

(SPDIF_ST_CLK) for SPDIF in Tx mode.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

Table 48. SPDIF timing parameters

Parameter

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIF_OUT output (Load = 50 pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT output (Load = 30 pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SPDIF_SR_CLK) period

srckp

40.0

—

SPDIF_SR_CLK high period

srckph

16.0

—

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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