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Table 68. RGMII signal switching specifications[1],[2],[3],[4]...continued
Symbol
Description
Min.
Max.
Unit
Duty_G
Duty cycle for Gigabit
45
55
%
Duty_T
Duty cycle for 10/100T
40
60
%
[1] The timings assume the following configuration: DSE[5:0] = 001111 and FSEL1[1:0] = 11.
[2] Measured as defined in
EIA/JESD 8-6 1995 with a timing threshold voltage of VDDQ/2.
[3] Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm, unterminated, 2-inch microstrip trace on
standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance in the transmission line should be matched closely to the selected RDSON of the I/O
pad output driver.
[4] RGMII timing specifications are only valid for 1.8 V nominal I/O pad supply voltage.
RGMII_TXC (at transmitter)
RGMII_TXDn (n = 0 to 3 )
RGMII_TX_CTL
RGMII_TXC (at receiver)
TskewT
TXEN
TXERR
TskewR
Figure 33. RGMII transmit signal timing diagram original
RGMII_RXC (at transmitter)
RGMII_RXDn (n = 0 to 3 )
RGMII_RX_CTL
RGMII_RXC (at receiver)
TskewT
RXDV
RXERR
TskewR
Figure 34. RGMII receive signal timing diagram original
4.12.4 LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with Controller and Peripheral operations.
Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI
timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and
a 25 pF maximum load on all LPSPI pins.
The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.
NXP Semiconductors
IMX93CEC
i.MX 93 Applications Processors Data Sheet for Commercial Products
IMX93CEC
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 7 — 12 February 2026
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